Philips Semiconductors
Single 2-input NAND gate
Product specification
74LVC1G00
SYMBOL
PARAMETER
TEST CONDITIONS
OTHER
VCC (V)
MIN.
TYP.(1)
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage
1.65 to 1.95 0.65 × VCC −
2.3 to 2.7 1.7
−
2.7 to 3.6 2.0
−
VIL
LOW-level input voltage
4.5 to 5.5 0.7 × VCC −
1.65 to 1.95 −
−
2.3 to 2.7 −
−
2.7 to 3.6 −
−
4.5 to 5.5 −
−
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA
1.65 to 5.5 −
−
IO = 4 mA
1.65
−
−
IO = 8 mA
2.3
−
−
IO = 12 mA
2.7
−
−
IO = 24 mA
3.0
−
−
IO = 32 mA
4.5
−
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
1.65 to 5.5 VCC − 0.1 −
IO = −4 mA
1.65
0.95
−
IO = −8 mA
2.3
1.7
−
IO = −12 mA
2.7
1.9
−
IO = −24 mA
3.0
2.0
−
IO = −32 mA
4.5
3.4
−
ILI
input leakage current
VI = 5.5 V or GND 5.5
−
−
Ioff
power OFF leakage
VI or VO = 5.5 V 0
current
−
−
ICC
quiescent supply current VI = VCC or GND; 5.5
−
−
IO = 0 A
∆ICC
additional quiescent
VI = VCC − 0.6 V; 2.3 to 5.5 −
−
supply current per pin IO = 0 A
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
MAX. UNIT
−
V
−
V
−
V
−
V
0.35 × VCC V
0.7
V
0.8
V
0.3 × VCC V
0.1
V
0.70
V
0.45
V
0.60
V
0.80
V
0.80
V
−
V
−
V
−
V
−
V
−
V
−
V
±100
µA
±200
µA
200
µA
5 000
µA
2004 Sep 07
7