Nexperia
74AHC1G00; 74AHCT1G00
2-input NAND gate
14. Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
74AHC_AHCT1G00 v.7 20141105
Product data sheet
-
Modifications:
• Section 4: table note added.
74AHC_AHCT1G00 v.6
74AHC_AHCT1G00 v.6
Modifications:
20070530
Product data sheet
-
74AHC_AHCT1G00 v.5
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Package SOT353 changed to SOT353-1 in Section 3 and Section 13.
• Quick reference data and Soldering sections removed.
74AHC_AHCT1G00 v.5 20020527
Product specification -
74AHC_AHCT1G00 v.4
74AHC_AHCT1G00 v.4 20020227
Product specification -
74AHC_AHCT1G00 v.3
74AHC_AHCT1G00 v.3 20010131
Product specification -
74AHC_AHCT1G00 v.2
74AHC_AHCT1G00 v.2 19990127
Product specification -
74AHC_AHCT1G00_N v.1
74AHC_AHCT1G00_N v.1 19981125
Preliminary specification -
-
74AHC_AHCT1G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 5 November 2014
© Nexperia B.V. 2017. All rights reserved
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