MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Timing Diagrams (Note 29)
Read Cycle
VIH
RAS
VIL
VIH
CAS
VIL
VIH
A0~A9
VIL
VIH
W
VIL
DQ1~DQ8 VIH
(INPUTS) VIL
DQ1~DQ8 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRC
tRAS
tRP
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tRAH
tRAD
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRAL
tRCS
tCRP
tRCH
tASR
tRRH
ROW
ADDRESS
tDZC
tCDD
Hi-Z
Hi-Z
tCAC
tAA
tCLZ
tOFF
tRAC
tDZO
DATA VALID
tOEA
tOCH
tOEZ
tODD
tORH
Hi-Z
Note 29
Indicates the don't care input.
VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max)
Indicates the invalid output.
8
M5M44800CJ,TP-5,-5S:Under development