MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Fast Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle) (Note 24)
Limits
Symbol
Parameter
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S Unit
Min Max Min Max Min Max
tPC
Fast page mode read/write cycle time
35
40
45
ns
tPRWC
Fast page mode read write/read modify write cycle time
71
80
95
ns
tRAS
RAS low pulse width for read or write cycle
(Note 25) 85 100000 100 100000 115 100000 ns
tCP
CAS high pulse width
(Note 26) 8
12
10
15
10
15
ns
tCPRH
RAS hold time after CAS precharge
30
35
40
ns
tCPWD
Delay time, CAS precharge to W low
(Note 23) 48
55
65
ns
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.
Note 25: tRAS(min) is specified as two cycles of CAS input are performed.
Note 26: tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle, Extended Refresh Cycle * (Note 27)
Symbol
Parameter
Limits
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S Unit
Min Max Min Max Min Max
tCSR
CAS setup time before RAS low
tCHR
CAS hold time after RAS low
tCAS
CAS low pulse width
5
5
5
ns
10
10
15
ns
20
20
25
ns
Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Self Refresh Cycle * (Note 28)
Symbol
Parameter
tRASS
tRPS
tCHS
CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time
Limits
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S Unit
Min Max Min Max Min Max
100
100
100
µs
90
110
130
ns
-50
-50
-50
ns
7
M5M44800CJ,TP-5,-5S:Under development