ENC424J600/624J600
FIGURE 1-1:
SO
CS/CS
SCK/AL
SI/RD/RW
AD<15:0>(1)
A<14:0>(1)
WR/WRL/
EN/B0SEL(1)
WRH/
B1SEL(1)
PSPCFGx(1)
SPISEL
ENC424J600/624J600 BLOCK DIAGRAM
I/O
Interface
Bus
Interface
Arbiter
m3
m0
m1
RX Control
Logic
RX Filter
DMA and
Checksum
m2
Memory
Control
Registers
SRAM
24 Kbytes
Crypto Cores
TX Control
Logic
Flow Control
Host Interface
MAC
MII
Interface
PHY
TX
RX
MIIM
Interface
Control Logic
Power-on
Reset
PLL
Voltage
Regulator
25 MHz
Oscillator
TPOUT+
TPOUT-
TPIN+
TPIN-
RBIAS
OSC1
OSC2
INT LEDA LEDB
CLKOUT
VCAP
Note 1: A<14:0>, AD15, WRL/B0SEL, WRH/B1SEL and PSPCFG<4:1> are available on 64-pin devices only. PSPCFG0 is available on 44-pin
devices only.
DS39935B-page 6
© 2009 Microchip Technology Inc.