
MC74HC76
SWITCHING WAVEFORMS
tw
tf
tr
Set or
Reset
50%
VCC
90%
Clock
50%
VCC
tPHL
GND
10%
tw
GND
Q or Q
50%
1/fMAX
tPLH
tPHL
tPLH
90%
Q or Q 50%
10%
tTLH
tTHL
Q or Q
50%
trec
VCC
Clock
50%
GND
Figure 1.
Figure 2.
Valid
VCC
J or K
50%
GND
tsu
th
VCC
Clock
50%
GND
Figure 3.
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
3,8
Reset
4,9
J
CL
CL
15,11
Q
16,12
K
CL
CL
CL
CL
CL
CL
CL
CL
CL
1,6
Clock
2,7
Set
CL
14,10
Q
CL
CL
Figure 5. Expanded Logic Diagram
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6