AD5761R/AD5721R
6.0
0nF
5.5
1nF
5nF
5.0
7nF
10nF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VTVADSSD===25–+⁰12C11VV
LOAD = 2kΩ
0
–3 –2 –1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TIME (µs)
Figure 55. Full-Scale Settling Time at Various Capacitive Loads,
0 V to 5 V Range
0.005
0.004
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
–0.004
–0.005
–0.006
–0.007
–0.008
–0.009
–0.010
0
VDD = 21V
VSS = –11V
LOAD = 2kΩ||200pF
TA = 25°C
0.5 1.0 1.5 2.0 2.5 3.0 3.5
TIME (µs)
Figure 56. Digital-to-Analog Glitch Energy, 5 V Range
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010
0
VDD = 21V
VSS = –11V
LOAD = 2kΩ||200pF
TA = 25°C
0.5 1.0 1.5 2.0 2.5 3.0 3.5
TIME (µs)
Figure 57. Digital-to-Analog Glitch Energy, ±10 V Range
10V
VDD
10V
5V
20mV
VSS
VREFIN/VREFOUT
VOUT
Data Sheet
2
20ms/DIV
Figure 58. Power-Up Glitch
5V
5V
SYNC
5V
SCLK
SDI
1V
VOUT
200µs/DIV
Figure 59. Software Full Reset Glitch from Full Scale with Output Loaded,
0 V to 5 V Range
5V
5V
SYNC
5V
SCLK
SDI
500mV
VOUT
200µs/DIV
Figure 60. Software Full Reset Glitch from Midscale with Output Loaded,
5 V Range
Rev. A | Page 20 of 35