BLOCK DIAGRAM
fin 8
fin 7
2
REFout
1
REFin
BUFFER
AND
CONTROL
3
32/33 OR
64/65
PRESCALER
RATIO
(INTERNAL) 2
23
A AND N COUNTERS
TO MUX FOR
OUTPUT A
18
2
BitGrabber Plus
A REGISTER
23 BITS
fV
PHASE/
FREQUENCY
DETECTOR
fR
PAIR
STBY
(INTERNAL)
3 LD
4
PDout/φR
5
Rx/φV
13–STAGE
R COUNTER
13
7
DOUBLE BUFFER
BitGrabber Plus
Rs
16
R REGISTER
16 BITS
Rs′
13
2
BitGrabber Plus
C REGISTER
7 BITS
UNUSED
2
UNUSED
2
BitGrabber Plus
C′ REGISTER
7 BITS
STBY′
(INTERNAL)
fin′ 13
fin′ 14
13–STAGE
R′ COUNTER
32/33 OR
64/65
PRESCALER
A′ & N′ COUNTERS
fR′
18
LD′
PHASE/
FREQUENCY 17
DETECTOR
PDout ′/φR′
fV′
PAIR
16 Rx ′/φV′
RATIO
23
2
(INTERNAL)
18
BitGrabber Plus
A′ REGISTER
23 BITS
PORT
fV′
fR′
23
2
UNUSED
fR
MUX
10
fV
ENB 11
Din 20
CLK 19
24 1/2 STAGE
SHIFT REGISTER
DATA OUT
ADDRESS 5
2
LOGIC AND
STORAGE
PLL / PLL′
PIN 9 = V+ (Positive Power to the main PLL, Reference Circuit, and a portion of the Serial Port)
PIN 6 = GND (Ground to the main PLL, Reference Circuit, and a portion of the Serial Port)
PIN 12 = V+′ (Positive Power to PLL′ and a portion of the Serial Port)
PIN 15 = GND′ (Ground to PLL′ and a portion of the Serial Port)
2
SELECT FROM
A REGISTER
(INTERNAL)
OUTPUT A
MC145220
2
MOTOROLA