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WT62P1-N42 View Datasheet(PDF) - Weltrend Semiconductor

Part Name
Description
MFG CO.
WT62P1-N42
Weltrend
Weltrend Semiconductor 
WT62P1-N42 Datasheet PDF : 48 Pages
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WT62P1
Data Sheet Rev. 1.01
DDC Receive Buffer Register
Name Addr R/W Initial Bit 7
DDC_RX 0014h R FFh DRX7
Bit 6
DRX6
Bit 5
DRX5
Bit4
DRX4
Bit 3
DRX3
Bit 2
DRX2
Bit 1
DRX1
Bit 0
DRX0
Bit Name
Description
DRX7 … DRX0 DDC received data is stored in this register.
DDC Transmit Buffer Register
Name Addr R/W Initial Bit 7
DDC_TX 0014h W FFh DTX7
Bit 6
DTX6
Bit 5
DTX5
Bit4
DTX4
Bit 3
DTX3
Bit 2
DTX2
Bit 1
DTX1
Bit 0
DTX0
Bit Name
Description
DTX7 … DTX0 This register stores the data to be transmitted
DDC Status Register
Name Addr R/W Initial Bit 7 Bit 6
DDC_STA 0015h R 01h DDCRDY SCLH2L
Bit 5
DDC2
Bit4 Bit 3
Bit 2
Bit 1 Bit 0
FIRST STOP DDC2RW MATCH RXNAK1
Bit Name
DDCRDY
SCLH2L
DDC2(R)
FIRST
STOP
DDC2RW
MATCH
RXNAK1
Description
When it is set, data buffer is ready to read/write or a SCL1 high to low transition in DDC1
state.
Indicates a high to low transition on SCL1 pin in DDC1 state when it is set.
“ 1” : Indicates it is in DDC2 state.
“ 0” : Indicates it is in DDC1 state.
Indicates the first byte (address) is received when this bit is set.
Indicates STOP condition is received when this bit is set.
Indicates the received R/W bit after 7-bit address.
“ 1” : Read
“ 0” : Write
“ 1” : Address is equal to Address Register 1.
“ 0” : The most significant 4 bits are equal to Address Register 0.
Indicates the received acknowledge bit.
“ 1” : NACK
“ 0” : ACK
DDC Control Register
Name Addr R/W Initial Bit 7 Bit 6 Bit 5 Bit4
DDC_CON 0015h W 00h ENDDC CLRH2L DDC2
--
Bit 3
--
Bit 2
TX
Bit 1 Bit 0
-- TXNAK1
Bit Name
ENDDC
CLRH2L
DDC2(W)
TX
TXNAK1
Description
“ 1” : Enable DDC interface. PA0 and PA1 are configured as DDC interface.
“ 0” : Disable DDC interface. PA0 and PA1 are configured as I/O port.
Set this bit will reset SCLH2L bit.
“ 1” : Set DDC2.
“ 0” : Set DDC1.
“ 1” : Set transmit direction.
“ 0” : Set receive direction.
Determines the ACK bit to be transmitted.
“ 1” : Transmit NACK.
“ 0” : Transmit ACK.
Weltrend Semiconductor, Inc.
Page 21

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