Production Data
WM8569
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
ADCBCLK/DACBCLK cycle
tBCY
time
ADCBCLK/DACBCLK pulse
tBCH
width high
ADCBCLK/DACBCLK pulse
tBCL
width low
ADCLRC/DACLRC set-up
time to
ADCBCLK/DACBCLK rising
edge
tLRSU
ADCLRC/DACLRC hold
tLRH
time from
ADCBCLK/DACBCLK rising
edge
DIN set-up time to
tDS
DACBCLK rising edge
DIN hold time from
tDH
DACBCLK rising edge
DOUT propagation delay
tDD
from ADCBCLK falling edge
Table 3 Digital Audio Data Timing – Slave Mode
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
0
10
ns
w
PD Rev 4.0 June 2006
11