V54C365804VDL-75 View Datasheet(PDF) - Mosel Vitelic Corporation

Part Name

Description

MFG CO.

V54C365804VDL-75

HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8

Mosel Vitelic Corporation  

MOSEL VITELIC

Timing Diagrams

1. Bank Activate Command Cycle

2. Burst Read Operation

3. Read Interrupted by a Read

4. Read to Write Interval

4.1 Read to Write Interval

4.2 Minimum Read to Write Interval

4.3 Non-Minimum Read to Write Interval

5. Burst Write Operation

6. Write and Read Interrupt

6.1 Write Interrupted by a Write

6.2 Write Interrupted by Read

7. Burst Write & Read with Auto-Precharge

7.1 Burst Write with Auto-Precharge

7.2 Burst Read with Auto-Precharge

8. Burst Termination

8.1 Termination of a Full Page Burst Write Operation

8.2 Termination of a Full Page Burst Write Operation

9. AC- Parameters

9.1 AC Parameters for a Write Timing

9.2 AC Parameters for a Read Timing

10. Mode Register Set

11. Power on Sequence and Auto Refresh (CBR)

12. Clock Suspension (using CKE)

12.1 Clock Suspension During Burst Read CAS Latency = 2

12. 2 Clock Suspension During Burst Read CAS Latency = 3

12. 3 Clock Suspension During Burst Write CAS Latency = 2

12. 4 Clock Suspension During Burst Write CAS Latency = 3

13. Power Down Mode and Clock Suspend

14. Self Refresh (Entry and Exit)

15. Auto Refresh (CBR)

V54C365804VD(L) Rev. 0.9 September 2001

15

V54C365804VD(L)

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