µ PD16347
3. PIN FUNCTIONS
Symbol
/LBLK
/HBLK
/LE
HZ
/CLR
A1 to A3 (6)
CLK
R,/L
IBS1,
IBS2
DET
SDS
O1 to O192
VDD1
VDD2
VDD3
VSS1
VSS2
VSS3
Pin Name
Low blanking
High blanking
Latch enable
Output high impedance
Register clear
Data
Clock
Shift direction control
Input mode switch
Temperature detection
Clock edge switch
High withstanding voltage
Logic power supply
Driver power supply
Temperature detection
power supply
Logic ground
Driver ground
Temperature detection
ground
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Output
−
−
−
Description
/LBLK = L: All output = L
/HBLK = L: All output = H
Latch operation performed at the falling edge.
HZ = H: All output set to the high-impedance state
/CLR = L: All shift register data cleared to the low level
The A1 to A3 (6) are Data input pins. The data shift direction is switched
inside the R,/L pin.
SDS = H: Shift operation is executed at the rising and falling edges
SDS = L: Shift operation is executed at the rising edge
The shift direction control pin of shift register. The shift directions of the
shift register are as follows.
R,/L = H (right shift):
SR1: A1 → S1...S190 (SR2 to SR6 also shift in the same direction.)
R,/L = L (left shift):
SR1: A1 → S190...S1 (SR2 to SR6 also shift in the same direction.)
Refer to 5. INTERNAL REGISTER.
IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input, Length of shift register: 32-bit
IBS1 = H, IBS2 = L: 6-bit input, Length of shift register: 32-bit
IBS1 = L, IBS2 = H: 3-bit input, Length of shift register: 64-bit
IBS1 = L, IBS2 = L: 4-bit input, Length of shift register: 48-bit
The DET is N-ch open-drain output. Low level is output (N-ch transistor:
ON) via temperature detection.
SDS = H: Shift operation is executed at the rising and falling edges of CLK
(double edge)
SDS = L: Shift operation is executed at the rising edge of CLK (single edge)
70 V
5 V ± 5%
15 to 70 V
5 V ± 10%
−
Connect to system ground
−
Connect to system ground
−
Connect to system ground
Caution In 3-bit and 4-bit input mode, unused input pins must be held at the low level or high level.
Data Sheet S16472EJ1V0DS
7