UJA1065 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

UJA1065

High-speed CAN/LIN fail-safe system basis chip

NXP Semiconductors. 

NXP Semiconductors

UJA1065

High-speed CAN/LIN fail-safe system basis chip

Table 2. Pin description …continued

Symbol Pin Description

INH/LIMP 17 inhibit/limp-home output (BAT14 related, push-pull, default floating)

WAKE

18 local wake-up input (BAT42 related, continuous or cyclic sampling)

n.c.

19 not connected

V2

20 5 V voltage regulator output for CAN; connect a buffer capacitor to this pin

CANH

21 CANH bus line (HIGH in dominant state)

CANL

22 CANL bus line (LOW in dominant state)

GND

23 ground

SPLIT

24 CAN-bus common mode stabilization output

LIN

25 LIN-bus line (LOW in dominant state)

RTLIN

26 LIN-bus termination resistor connection

BAT14

27 14 V battery supply input

n.c.

28 not connected

SYSINH 29 system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC

converter)

V3

30 unregulated 42 V output (BAT42 related; continuous output, or Cyclic mode

synchronized with local wake-up input)

SENSE 31 fast battery interrupt / chatter detector input

BAT42

32 42 V battery supply input (connect this pin to BAT14 in 14 V applications)

The exposed die pad at the bottom of the package allows better dissipation of heat from

the SBC via the printed-circuit board. The exposed die pad is not connected to any active

part of the IC and can be left floating, or can be connected to GND for the best EMC

performance.

UJA1065_7

Product data sheet

Rev. 07 — 25 February 2010

© NXP B.V. 2010. All rights reserved.

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