EVAL1002/AA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
EVAL1002/AA Datasheet PDF : 20 Pages
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N TSA1002 APPLICATION NOTE
DETAILED INFORMATION
The TSA1002 is a high speed analog to digital
converter based on a pipeline architecture and the
latest deep submicron CMOS process to achieve
the best performances in terms of linearity and
power consumption.
The pipeline structure consists of 9 internal
G couple for each stage. The corrected data are
I outputted through the digital buffers.
Input signal is sampled on the rising edge of the
S clock while digital outputs are delivered on the
falling edge of the Data Ready signal.
E The advantages of such a converter reside in the
combination of pipeline architecture and the most
D advanced technologies. The highest dynamic
conversion stages in which the analog signal is performances are achieved while consumption
fed and sequentially converted into digital data.
Each 8 first stages consists of an Analog to Digital
W converter, a Digital to Analog converter, a Sample
and Hold and a gain of 2 amplifier. A 1.5bit
E ) conversion resolution is achieved in each stage.
t(s The latest stage simply is a comparator. Each
N c resulting LSB-MSB couple is then time shifted to
u recover from the conversion delay. Digital data
d correction completes the processing by
R ro recovering from the redundancy of the (LSB-MSB)
remains at the lowest level.
Some functionalities have been added in order to
simplify as much as possible the application
board. These operational modes are described in
the following table.
The TSA1002 is pin to pin compatible with the
8bits/40Msps TSA0801, the 10bits/25Msps
TSA1001 and the 12bits/50Msps TSA1201. This
ensures a conformity within the product family and
above all, an easy upgrade of the application.
O te P OPERATIONAL MODES DESCRIPTION
le Inputs
F so Analog input differential level
DFSB OEB OR DR
b (VIN-VINB)
>
RANGE
H
T O -RANGE
>
(VIN-VINB)
H
) - RANGE> (VIN-VINB) >-RANGE
H
O t(s (VIN-VINB)
>
RANGE
L
-RANGE
>
(VIN-VINB)
L
N uc RANGE> (VIN-VINB) >-RANGE
L
d X
X
L
H CLK
L
H CLK
L
L CLK
L
H CLK
L
H CLK
L
L CLK
H
HZ HZ
Outputs
Most Significant Bit (MSB)
D9
D9
D9
Complemented D9
Complemented D9
Complemented D9
HZ
Pro Data Format Select (DFSB)
te When set to low level (VIL), the digital input DFSB
le provides a twoís complement digital output MSB.
o This can be of interest when performing some
sfurther signal processing.
ObWhen set to high level (VIH), DFSB provides a
When OEB is set to low level again, the data is
then valid on the output with a very short Ton
delay.
The timing diagram page 4 summarizes this
operating cycle.
Out of Range (OR)
standard binary output coding.
This function is implemented on the output stage
Output Enable (OEB)
in order to set up an "Out of Range" flag whenever
the digital data is over the full scale range.
When set to low level (VIL), all digital outputs Typically, there is a detection of all the data being
remain active and are in low impedance state. at í0í or all the data being at í1í. This ends up with
When set to high level (VIH), all digital outputs an output signal OR which is in low level state
buffers are in high impedance state. This results in (VOL) when the data stay within the range, or in
lower consumption while the converter goes on high level state (VOH) when the data are out of the
sampling.
range.
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