AD7716BS View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7716BS Datasheet PDF : 16 Pages
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AD7716
SLAVE MODE TIMING CHARACTERISTICS1, 2 (AVDD= DVDD = +5 V ؎ 5%; AVSS = –5 V ؎ 5%; AGND = DGND = 0 V;
fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Parameter
(B Version)
Units
Conditions/Comments
fCLKIN3, 4
tr5
tf5
t23
t24
t25
t26
t27
t286
t29
t307
t31
t32
400
8
40
40
1/fCLKIN
50
125
1/fCLKIN +30
30
50
50
50
0
60
2/fCLKIN
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns max
CLKIN Frequency
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
CASCIN Pulse Width
SCLK Width
SCLK Period
CASCIN High to RFS Setup Time
RFS Low to SCLK High Setup Time
SCLK High to SDATA Valid Delay
RFS Hold Time After SCLK High
SCLK High to SDATA High Impedance Delay
SCLK High to CASCOUT High Delay.
CASCOUT Pulse Width
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 and 4.
3CLKIN duty cycle range is 40% to 60%.
4The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz.
5Specified using 10% and 90% points on waveform of interest.
6t28 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7t30 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
CASCIN (I)
SCLK (I)
RFS (I)
SDATA (O)
CASCOUT (O)
t23
t 26
t 24
t25
t 24
t 27
t29
t 28
t30
DB31
DB30 DB29
DB28 DB27 DB2
DB1
DB0
CH1
CH1
CH1
CH1
CH1 CH4
CH4
CH4
t31
t32
Figure 4. Slave Mode Timing Diagram
REV. A
–5–
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