TMC2081 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
TMC2081 Datasheet PDF : 32 Pages
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PRODUCT SPECIFICATION
TMC2081
Functional Description
The TMC2081 is a monolithic digital video processor that
proportionally mixes digital video in GBR, YCBCR, or color-
index formats. Some of the variety of input and output data
format combinations are shown in Table 1.
The A-channel data path has transformation circuits that can
look up 24-bit GBR values from 8-bit color-index inputs,
convert GBR-to-YCBCR format, and decimate YCBCR444 to
YCBCR422. The B-channel path includes circuits that
convert YCBCR to GBR and interpolate YCBCR422 to
YCBCR444. Prior to mixing, incoming pixel data streams
must be converted to matching formats by setting the A and
B channel control registers.
Data enters the TMC2081 through the PDA23-0, PDB23-0,
a8-0, and OL3-0 ports. Data and video controls (PASSEN and
AV) are simultaneously registered on the rising edge of
PXCLK. Pipeline latency is 14 clock cycles to the mixed
digital video output.
Although PDA23-0, PDB23-0, and M23-0 data formats may be
different, V1 and V2 data formats at the a-Mixer input must
be matched: unsigned magnitude for GBR and Y
components; 2’s complement for CB and CR components.
Data formats converted within the TMC2081 are determined
by the control bits programmed into the internal registers.
Output format may be GBR, YCBCR444 or YCBCR422.
Either crosspoint switch input, A and B or the Mixer output
may be selected at the M23-0 port. Table 2, Table 3 and Table
4 show examples of the M23-0 output for 9-bit a-mixing. In
Table 3, CBCR is accepted at the CB input. Table 4 exempli-
fies format
conversion.
Mixer output and inputs may be previewed by three video
D/A converters. Analog outputs may be either GBR or
YCBCR.
For initialization and control, internal registers and tables
may be accessed through a microprocessor interface.
Power may be conserved by disabling the D/A converters or
sections of the TMC2081 via internal Control Registers.
In the latter mode, the microprocessor interface remains
active and Control Register settings are retained but CLUT
locations are not accessible.
Table 1. Input and Output Data Format Examples
A Input
Format
YCBCR444
YCBCR444
YCBCR444
YCBCR422
YCBCR422
GBR, CI
GBR, CI
GBR, CI
GBR, CI
GBR, CI
B Input
A
A
Format CLUT GBR-YCBCR
YCBCR444 Bypass Bypass
YCBCR422 Bypass Bypass
YCBCR422 Bypass Bypass
YCBCR422 Bypass Bypass
YCBCR422 Bypass Bypass
YCBCR444 Enable Bypass
YCBCR444 Enable Enable
YCBCR422 Enable Bypass
YCBCR422 Enable Enable
GBR Enable Bypass
A
Decimate
Bypass
Bypass
Enable
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
B
B
Interpolate YCBCR-GBR
Bypass
Bypass
Enable
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Enable
Bypass
Bypass
Enable
Enable
Bypass
Bypass
Bypass
Bypass
M
Format
Low
Low
High
High
Low
Low
Low
Low
High
Low
M Output
Format
YCBCR444
YCBCR444
YCBCR422
YCBCR422
YCBCR444
GBR
YCBCR444
GBR
YCBCR422
GBR
Table 2. GBR Mixing Example (9-bit a)
a
(hex)
PDA (hex)
G
B
R
000
BB
CC
AA
040
BB
CC
AA
080
BB
CC
AA
100
BB
CC
AA
PDB (hex)
G
B
R
EE
FF
DD
EE
FF
DD
EE
FF
DD
EE
FF
DD
M (hex)
G
B
R
EE
FF
DD
E1
F2
D0
D5
E6
C4
BB
CC
AA
3
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