T89C51RD2-3CSIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
T89C51RD2-3CSIM Datasheet PDF : 104 Pages
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T89C51RD2
Table 2. Pin Description (Continued)
Pin Number
Mnemonic
DIL LCC VQFP 1.4
12
14
8
13
15
9
14
16
10
15
17
11
16
18
12
17
19
13
Reset
9
10
4
ALE/PROG
30
33
27
PSEN
EA
XTAL1
XTAL2
29
32
26
31
35
29
19
21
15
18
20
14
Type Name and Function
I INT0 (P3.2): External interrupt 0
I INT1 (P3.3): External interrupt 1
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to VSS permits a power-on reset using only an
external capacitor to VCC. This pin is an output when the hardware watchdog forces a
system reset.
O (I)
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory. This pin is also the program pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE
will be inactive during internal fetches.
O Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
I External Access Enable: EA must be externally held low to enable the device to fetch
code from external program memory locations 0000H to FFFFH (RD). If security level
1 is programmed, EA will be internally latched on Reset.
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
O Crystal 2: Output from the inverting oscillator amplifier
7
4243G–8051–05/03
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