STA323WTR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STA323WTR

2.1 HIGH EFFICIENCY DIGITAL AUDIO SYSTEM

STMicroelectronics 

STA323W

7.7.3 Binary Clock Loss Detection Enable

BIT

R/W

RST

NAME

DESCRIPTION

5

R/W

1

BCLE

Binary Output Mode Clock Loss Detection Enable

0 – Disabled

1 – Enabled

Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when

input clocking is lost.

7.7.4 Auto-EAPD on Clock Loss Enable

BIT

R/W

RST

NAME

DESCRIPTION

7

R/W

0

ECLE

Auto EAPD on Clock Loss

0 – Disabled

1 – Enabled

When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection.

7.7.5 External Amplifier Power Down

BIT

R/W

RST

NAME

DESCRIPTION

7

R/W

0

EAPD External Amplifier Power Down:

0 – External Power Stage Power Down Active

1 – Normal Operation

EAPD is used to actively power down a connected DDX® Power device. This register has to be written to

1 at start-up to enable the DDX® power device for normal operation.

7.8 VOLUME CONTROL

7.8.1 Master Controls

7.8.1.1Master Mute Register (Address 06h)

D7

D6

D5

D4

D3

D2

D1

D0

MMUTE

0

7.8.1.2Master Volume Register (Address 07h)

D7

D6

D5

D4

D3

D2

MV7

MV6

MV5

MV4

MV3

MV2

1

1

1

1

1

1

Note : Value of volume derived from MVOL is dependent on AMV AutoMode Volume settings.

7.8.2 Channel Controls

7.8.2.1Channel 1 Volume (Address 08h)

D7

C1V7

0

D6

C1V6

1

D5

C1V5

1

D4

C1V4

0

D3

C1V3

0

D2

C1V2

0

D1

MV1

1

D1

C1V1

0

D0

MV0

1

D0

C1V0

0

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