ST7PMC2N2T3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7PMC2N2T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

Table 2. Hardware Register Map

Address

Block

Register

Label

Register Name

Reset

Status

Remarks

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

ITSPR0

Interrupt Software Priority Register 0

ITSPR1

Interrupt Software Priority Register 1

ITC

ITSPR2

Interrupt Software Priority Register 2

ITSPR3

Interrupt Software Priority Register 3

EICR

External Interrupt Control Register

FFh

R/W

FFh

R/W

FFh

R/W

FFh

R/W

00h

R/W

FLASH

FSCR

Flash Control/Status Register

00h

R/W

WATCHDOG

WDGCR

WDGWR

Window Watchdog Control Register

Window Watchdog Window Register

7Fh

R/W

7Fh

R/W

MCC

MCCSR

Main Clock Control / Status Register

00h

R/W

MCCBCR Main Clock Controller: Beep Control Register 00h

R/W

ADC

ADCCSR Control/Status Register

ADCDRMSB Data Register MSB

ADCDRLSB Data Register LSB

00h

R/W

00h

Read Only

00h

Read Only

TIMER A

TACR2

TACR1

TACSR

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

TACLR

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Timer A Control Register 2

Timer A Control Register 1

Timer A Control/Status Register

Timer A Input Capture 1 High Register

Timer A Input Capture 1 Low Register

Timer A Output Compare 1 High Register

Timer A Output Compare 1 Low Register

Timer A Counter High Register

Timer A Counter Low Register

Timer A Alternate Counter High Register

Timer A Alternate Counter Low Register

Timer A Input Capture 2 High Register

Timer A Input Capture 2 Low Register

Timer A Output Compare 2 High Register

Timer A Output Compare 2 Low Register

00h

R/W

00h

R/W

xxh

R/W

xxh

Read Only

xxh

Read Only

80h

R/W

00h

R/W

FFh

Read Only

FCh Read Only

FFh

Read Only

FCh Read Only

xxh

Read Only

xxh

Read Only

80h

R/W

00h

R/W

SIM

SICSR

System Integrity Control/Status Register

000x000x b R/W

TIMER B

TBCR2

TBCR1

TBCSR

TBIC1HR

TBIC1LR

TBOC1HR

TBOC1LR

TBCHR

TBCLR

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

Timer B Control Register 2

Timer B Control Register 1

Timer B Control/Status Register

Timer B Input Capture 1 High Register

Timer B Input Capture 1 Low Register

Timer B Output Compare 1 High Register

Timer B Output Compare 1 Low Register

Timer B Counter High Register

Timer B Counter Low Register

Timer B Alternate Counter High Register

Timer B Alternate Counter Low Register

Timer B Input Capture 2 High Register

Timer B Input Capture 2 Low Register

Timer B Output Compare 2 High Register

Timer B Output Compare 2 Low Register

00h

R/W

00h

R/W

xxh

R/W

xxh

Read Only

xxh

Read Only

80h

R/W

00h

R/W

FFh

Read Only

FCh Read Only

FFh

Read Only

FCh Read Only

xxh

Read Only

xxh

Read Only

80h

R/W

00h

R/W

19/309

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