Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282
SST32HF1622C / SST32HF1642C / SST32HF3242C
Preliminary Specifications
ADDRESSES AMSS3-0
WE#
BES1#
TWCS
TWPS
TBWS
TWRS
BES2
TASTS
TBWS
TAWS
TBYWS
UBS#, LBS#
TDSS
TDHS
DQ15-8, DQ7-0
NOTE 2
VALID DATA IN
NOTE 2
1253 F05.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
AMSS = A16 for SST32HF1622C, A17 for SST32HFxx42x, and A18 for SST32HFxx82
FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
©2005 Silicon Storage Technology, Inc.
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S71253-03-000
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