SPT7850SCN View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
SPT7850SCN Datasheet PDF : 13 Pages
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Figure 1A – Timing Diagram 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
ANALOG IN
CLOCK IN
SAMPLING CLOCK
(Internal)
DIGITAL OUT
INVALID
VALID
1 2 3 4 5 6 7 8 9 10 11
DATA VALID
Figure 1B – Timing Diagram 2
tC
tCH
tCL
tCLK
CLOCK
IN
tOD
DATA
OUTPUT
Data 0
Data 1
DATA
VALID
tS
tDAV
tDAV
Data 2
Table I – Timing Parameters
DESCRIPTION
PARAMETERS
Conversion Time
tC
Clock Period
tCLK
Clock High Duty Cycle
tCH
Clock Low Duty Cycle
tCL
Clock to Output Delay (15 pF Load)
tOD
DAV Pulse Width
tDAV
Clock to DAV
tS
MIN
2*tCLK
25
40
40
15
16
TYP
50
50
20
tCLK
21
MAX
60
60
25
26
UNITS
ns
ns
%
%
ns
ns
ns
SPT7850
5
6/15/01
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