SP9602KS View Datasheet(PDF) - Signal Processing Technologies
Part Name
Description
MFG CO.
SP9602KS Datasheet PDF : 11 Pages
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SPECIFICATIONS (continued)
(Typical at 25˚C, TMIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN. TYP. MAX.
UNITS
CONDITIONS
STABILITY
Gain
15
Bipolar Zero
15
SWITCHING CHARACTERISTICS
tDS Data Set Up Time
140
100
tDN Data Hold Time
0
tWR Write Pulse Width
140
100
tXFER Transfer Pulse Width
140
tWC Total Write Command
280
200
POWER REQUIREMENTS
VDD
–J, –K
1.6
2.5
VSS
–J, –K
1.6
2.5
Power Dissipation
16
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
-J, -K
Storage
Packages
–_N
–_S
0
+70
-60
+150
28–pin Plastic DIP
28–pin SOIC
ppm/˚C
ppm/˚C
ns
ns
ns
ns
ns
mA
mA
mW
°C
°C
t to t MIN
MAX
t to t
MIN
MAX
to rising edge of WR1
Figure 4
Note 5
+5V, +3%; Note 4, 5
–5V, +3%; Note 4, 5
Notes:
1.
2.
3.
4.
Integral Linearity, for the SP9602, is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
1 LSB = 2*VREF/4,096.
VREF = 0V.
5.
The following power up sequence is recommended to avoid latch up: VSS (-5V), VDD (+5V), REFIN.
0
INLE, DNLE Plots
CODE
+0.25 lsb
DNLE
-0.25 lsb
+0.25 lsb
INLE
-0.25 lsb
4095
SP9602DS/02
SP9602 Dual, 12-Bit, Low Power Voltage Output D/A Converter
3
© Copyright 1999 Sipex Corporation
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