MC92500ZQ View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

MFG CO.

MC92500ZQ

ATM Cell Processor

Motorola => Freescale 

5.4.1 Control Signals

These signals are used to control the MC92500.

ATMC Power-Up Reset (ARST)

This input signal is used for power-up reset of the

entire chip. It must be asserted for at least the time re-

quired by the PLL to lock.

Enable IDD (ENID)

This input is a dedicated test signal which must be

grounded during normal system operation.

ATMC Mode (AMODE0-AMODE1)

These inputs are dedicated test signals which

must be grounded during normal system operation.

5.4.2 Microprocessor Signals (MP)

The following signals relate to the microprocessor

interface.

MP Clock (MCLK)

This input signal is used as the Microprocessor

clock inside the MC92500. This signal drives the micro-

processor interface logic in the MC92500. The duty cy-

cle should be in the range of 40-60%.

MP Data Bus (MDATA0-MDATA31)

This 3-state bidirectional bus provides the general

data path between the MC92500 and the microproces-

sor.

MP Address Bus (MADD2-MADD25)

This input bus contains the address which is used

by the microprocessor to define the register being ac-

cessed. This bus is used by the MC92500 at the asser-

tion of MSEL and sampled on the falling edge of MCLK.

MP Select (MSEL)

This input signal is used to determine that the cur-

rent access to the MC92500 is valid. This signal is ac-

tive low and sampled by the MC92500 on the falling

edge of MCLK.

MP Data Select (MDS)

This input signal is used to indicate when the data

on MDATA is valid during a write access to the

MC92500. This signal is active low and sampled by the

MC92500 on the falling edge of MCLK.

MP Write (MWR)

This input signal is used to determine whether the

MP is reading from the MC92500 or writing to it. This

signal is active low and sampled by the MC92500 on

the falling edge of MCLK. The MC92500 will drive

MDATA when MSEL = 0 and MWR = 1.

MP Word Select High (MWSH)

This input signal indicates that the high word is be-

ing accessed. During a maintenance access, the value

detected on MWSH is driven on the appropriate

EMBSH signal. This signal is active low and sampled

by the MC92500 on the falling edge of MCLK.

MP Word Select Low (MWSL)

This input signal indicates that the low word is be-

ing accessed. During a maintenance write access, the

value detected on MWSL is driven on the appropriate

EMBSL signal. This signal is active low and sampled by

the MC92500 on the falling edge of MCLK.

Note: All Cell Extraction Register, Cell Insertion

Register, and General Register accesses are

long-word (32-bit) accesses, so both MWSH and

MWSL should be asserted low for these

accesses.

MP Data Acknowledge (MDTACK)

This three-state output signal is used to indicate

when the data on MDATA is valid during a read access

from the MC92500 or when the data has been sampled

during a write access to the MC92500. At the end of

each access, this signal is actively pulled up and then

3-stated (Hi -Z). The user may program the MC92500

not to drive MDTACK during certain types of accesses.

This signal is active low and is output asynchronously

to MCLK.

MP Interrupt (MINT)

This output signal is used to notify the micropro-

cessor of the occurrence of interrupting events. This

signal is asserted on the rising edge of ACLK (asyn-

chronous with respect to MCLK).

MP Cell In Request (MCIREQ)

This output signal may be used by an external

DMA device as a control line indicating when to start a

new cell insertion cycle into the MC92500. This signal

is asserted whenever the Cell Insertion Register array

is available to be written. This signal is active low and is

output on the falling edge of MCLK.

MOTOROLA

16

MC92500

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