CXD1812 View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
MFG CO.
CXD1812 Datasheet PDF : 56 Pages
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CXD1812Q/R
2-45. RESERVED (address 34HEX)
2-46. CADRC-H, M, L (sub CPU address counter - high, middle, low) register (address 35 to 37HEX)
The addresses are set by this register when the sub CPU accesses the buffer memory. The register value is
incremented if the data concerned are read from the buffer memory or are written into it.
2-47. RESERVED (address 38 to 3BHEX)
2-48. CLRINT0 (clear interrupt status 0) register (address 3CHEX)
When each bit of this register is set high, the corresponding interrupt status is cleared. The bit is automatically
set low after its interrupt status has been cleared. Therefore, there is no need for the sub CPU to reset to low.
bit 7:
DECINT (Decoder Interrupt)
bit 6:
DECTOUT (Decoder Timeout)
bit 5:
DRVOVRN (Drive Overrun)
bit 4:
SUBCSYNC (Subcode Sync)
bit 3, 2: RESERVED
bit 1:
SOFTRST (SRST Detected)
bit 0:
HARDRST (HRST Detected)
2-49. CLRINT1 (clear interrupt status 1) register (address 3DHEX)
When each bit of this register is set high, the corresponding interrupt status is cleared. The bit is automatically
set low after its interrupt status has been cleared. Therefore, there is no need for the sub CPU to reset to low.
bit 7:
PFIFOFUL (Packet FIFO Full)
bit 6:
RESERVED
bit 5:
RSTCMD (Reset Command)
bit 4:
STSREAD (Host Status Read)
bit 3:
HSTCMD (Host Command)
bit 2:
PIONG (PIO Transfer NG)
bit 1:
XFRSTOP (Transfer Stop)
bit 0:
BLXFRCMP (Block Transfer Complete)
2-50. INTEN0 (interrupt enable 0) register (address 3EHEX)
When each bit of this register is set high, the interrupt request to the sub CPU by the corresponding interrupt
status is enabled. (That is, the XINT pin becomes active in the interrupt status.) Each bit value of this register
has no effect on the corresponding interrupt status.
bit 7:
DECINT (Decoder Interrupt)
bit 6:
DECTOUT (Decoder Timeout)
bit 5:
DRVOVRN (Drive Overrun)
bit 4:
SUBCSYNC (Subcode Sync)
bit 3, 2: RESERVED
bit 1:
SOFTRST (SRST Detected)
bit 0:
HARDRST (HRST Detected)
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