CXD1812 View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
MFG CO.
CXD1812 Datasheet PDF : 56 Pages
| |||
CXD1812Q/R
bit 2, 1:
RFRSCTL1, 0 (refresh control 1, 0)
The refresh interval of the DRAM can be controlled by these bits. Set these bits according to the
clock frequency of XTL1. The refresh interval is designed as 512 cycle/8ms.
RFRSCTL1
"L"
"L"
"H"
"H"
RFRSCTL0
"L"
"H"
"L"
"H"
XTL1 frequency: less than 24MHz
XTL1 frequency: 24MHz or more
XTL1 frequency: 32MHz or more
XTL1 frequency: 33.8688MHz or more
bit0
RESERVED
2-3. LSTARA (last area) register (address 02HEX)
The last area is assigned by this register.
The following table shows the set values of LASTARA when the buffer memory is fully used.
ENBYTFBT
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
RAM size
32KB
64KB
128KB
256KB
512KB
LASTARAHEX
0C
0A
19
16
34
2E
69
5E
D3
BD
2-4. LHADR (last HADRC) register (address 03HEX)
Assigns the upper limit (upper 8 bits) of HADRC when the automatic transfer mode to the host is disabled, or
the upper limit (upper 8 bits) of the address when the row subcode buffering command is executed. The lower
11 bits are assigned to 7FFHEX.
2-5. DRVIF (drive interface) register (address 04HEX)
This register controls the connection mode with the CD DSP. After the IC is reset, the sub CPU sets this
register according to the CD DSP to be connected.
Any change of each bit in this register must be made in the decoder disable status. (After the IC is reset, the
address is set 28HEX.)
Figs. 1-1 and 1-2 are input timing charts for Sony's typical CD DSP.
– 19 –
Share Link: 