SC26C92A1B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
SC26C92A1B Datasheet PDF : 31 Pages
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Philips Semiconductors
Dual universal asynchronous receiver/transmitter (DUART)
Product specification
SC26C92
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions. The reserved
registers at addresses H‘02’ and H‘0A’ should never be read during
normal operation since they are reserved for internal diagnostics.
Table 1. SC26C92 Register Addressing
A3
A2
A1
A0
READ (RDN = 0)
WRITE (WRN = 0)
0
0
0
0
Mode Register A (MR0A, MR1A, MR2A)
Mode Register A (MR0A, MR1A, MR2A)
0
0
0
1
Status Register A (SRA)
Clock Select Register A (CSRA)
0
0
1
0
Reserved
Command Register A (CRA)
0
0
1
1
Rx Holding Register A (RxFIFOA)
Tx Holding Register A (TxFIFOA)
0
1
0
0
Input Port Change Register (IPCR)
Aux. Control Register (ACR)
0
1
0
1
Interrupt Status Register (ISR)
Interrupt Mask Register (IMR)
0
1
1
0
Counter/Timer Upper Value (CTU)
C/T Upper Preset Value (CTPU)
0
1
1
1
Counter/Timer Lower Value (CTL)
C/T Lower Preset Value (CTPL)
1
0
0
0
Mode Register B (MR0B, MR1B, MR2B)
Mode Register B (MR0B, MR1B, MR2B)
1
0
0
1
Status Register B (SRB)
Clock Select Register B (CSRB)
1
0
1
0
Reserved
Command Register B (CRB)
1
0
1
1
Rx Holding Register B (RxFIFOB)
Tx Holding Register B (TxFIFOB)
1
1
0
0
User Defined Flag/Status Flag
User Defined Flag/Status Flag
1
1
0
1
Input Ports IP0 to IP6
Output Port Conf. Register (OPCR)
1
1
1
0
Start Counter Command
Set Output Port Bits Command (SOP12)
1
1
1
1
Stop Counter Command
Reset Output Port Bits Command (ROP12)
NOTE:
The three MR Registers are accessed via the MR Pointer and Commands 1xh and Bxh. (Where “x” represents receiver and transmitter enable/
disable control)
The following named registers are the same for Channels
A and B
Mode Register
MRnA
MRnB
R/W
Status Register
SRA
SRB
R only
Clock Select
CSRA
CSRB
W only
Command Register
CRA
CRB
W only
Receiver FIFO
RxFIFOA RxFIFOB R only
Transmitter FIFO
TxFIFOA TxFIFOB W only
These registers control the functions which service both
Channels
Input Port Change Register
IPCR
R
Auxiliary Control Register
ACR
W
Interrupt Status Register
ISR
R
Interrupt Mask Register
IMR
W
Counter Timer Upper Value
CTU
R
Counter Timer Lower Value
CTL
R
Counter Timer Preset Upper
CTPU
W
Counter Timer Preset Lower
CTPL
W
Input Port Register
IPR
R
Output Configuration Register
OPCR
W
Set Output Port Bits
SOPR
W
Reset Output Port Bits
ROPR
W
Table 2. Register Bit Formats
BIT 7
BIT 6
MR0A, MR0B
MR0B[3:0] are
reserved
Returns F on read
Rx WATCH
DOG
0 = Disable
1 = Enable
RxINT BIT 2
See Tables in
MR0 description
BIT 5 BIT 4
TxINT (1:0)
BIT 3
DON’T
CARE
Set to 0
Returns 1 on read
BIT 2
BAUD RATE
EXTENDED II
0 = Normal
1 = Extend II
BIT 1
TEST 2
Set to 0
BIT 0
BAUD RATE
EXTENDED 1
0 = Normal
1 = Extend
MR1A
MR1B
0x00
BIT 7
Rx CONTROLS
RTS
BIT 6
Rx INT
BIT 1
0 = No
1 = Yes
0 = RxRDY
1 = FFULL
BIT 5
ERROR
MODE
0 = Char
1 = Block
BIT 4
BIT 3
PARITY MODE
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
BIT 2
PARITY
TYPE
0 = Even
1 = Odd
BIT 1
BIT 0
BITS PER
CHARACTER
00 = 5
01 = 6
10 = 7
11 = 8
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
2000 Jan 31
13
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