SC1175 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

MFG CO.

SC1175

Low Power Dual Synchronous DC/DC Controller With Current Sharing Circuitry

Semtech Corporation 

SC1175

POWER MANAGEMENT

Applications Information - Theory of Operation

their own current limits, identical to the independent 3. For high duty cycle on the slave channel (above 50%),

channel case.

the pull up will be on pin 2.

Power Good

The controller provides a power good signal. This is an

open collector output, which is pulled low if the output

voltage is outside of the power good window.

Soft Start/Enable

The formula is:

Rpull −up

(KΩ) = 2.1

X

.5

5

−

− VOUT

VOUT + .1

VSLAVE

100Ω being the value of the resistors connecting the

pins 2 and 3 to the two output sense resistors.

The Soft Start/Enable (SS/ENA) pin serves several func-

tions. If held below the Soft Start Enable threshold, both

channels are inhibited. DH1 and DH2 will be low, turning

off the top FETs. Between the Soft Start Enable thresh-

old and the Soft Start End threshold, the duty cycle is

allowed to increase. At the Soft Start End threshold,

maximum duty cycle is reached. In practical applications

the error amplifier will be controlling the duty cycle be-

fore the Soft Start End threshold is reached. To avoid

boost problems during startup in current share mode,

both channels start up in asynchronous mode, and the

bottom FET body diode is used for recirculating current

during the FET off time. When the SS/ENA pin reaches

the Soft Start Transition threshold, the channels begin

operating in synchronous mode for improved efficiency.

The soft start pin sources approximately 25uA and soft

start timing can be set by selection of an appropriate

soft start capacitor value.

SENSE RESISTOR SELECTION

Current Sharing Mode

Calculation of the three programming resistors to achieve

sharing. Three resistors will determine the current shar-

ing load line. First the offset resistor will ensure that the

load line crosses the origin (0 Amp on each channel) for

sharing at light current. A pull up resistor from the 5V

bias (VCC of the chip) will be used. For low duty cycle on

the slave channel (below 50%), the pull up will be on pin

.1 V is an estimated voltage drop across the MOSFETs.

Positive values go to pin 3, negative to pin 2.

A +20K will be a 20K on pin 3.

A -20K will be a 20K on pin 2.

Now that the offset resistor has been fixed, we need to

set up the maximum current for each channel.

Selection of RSENSE 1 for the master channel: (in m ohm)

RSENSE 1 = 72mV / I max master

Selection of RSENSE 2 for the slave channel: (in m ohm)

RSENSE 2 = 72mV / I max slave

The errors will be minimized if the power components

have been sized proportionately to the maximum

currents.

Independent Channels

Calculation of the two current limiting resistors.

There is no need for an offset resistor in the indepen-

dent channels mode, only the two sense resistors are

used:

Selection of RSENSE 1 for the channel 1: (mohms)

RSENSE 1 = 72mV / I max ch 1

Selection of RSENSE 2 for the channel 2: (mohms)

RSENSE 1 = 72mV / I max ch 2

 2004 Semtech Corp.

7

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