QL4009-2PL68C(2003) View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL4009-2PL68C
(Rev.:2003)
(Rev.:2003)
QuickLogic Corporation
QL4009-2PL68C Datasheet PDF : 18 Pages
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QL4009 QuickRAM Data Sheet Rev C
Symbol
tI/O
tISU
tIH
tIOCLK
tIORST
tIESU
tIEH
Table 7: I/O Cell Input Delays
Parameter
Propagation Delays (ns)
Fanouta
1 2 3 4 8 10
Input Delay (bidirectional pad)
1.3 1.6 1.8 2.1 3.1 3.6
Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
Input Register Clock to Q
0.7 1.0 1.2 1.5 2.5 3.0
Input Register Reset Delay
0.6 0.9 1.1 1.4 2.4 2.9
Input Register Clock Enable Set-Up Time
2.3 2.3 2.3 2.3 2.3 2.3
Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
Symbol
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Table 8: I/O Cell Output Delays
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
3
50
75
100 150
Output Delay Low to High
2.1 2.5 3.1 3.6 4.7
Output Delay High to Low
2.2 2.6 3.2 3.7 4.8
Output Delay Tri-state to High
1.2 1.7 2.2 2.8 3.9
Output Delay Tri-state to Low
1.6 2.0 2.6 3.1 4.2
Output Delay High to Tri-statea
Output Delay High to Tri-statea
2.0
-
-
-
-
1.2
-
-
-
-
a. The following loads are used for tPXZ
1K Ω
t PHZ
5 pF
1K Ω
tPLZ
5 pF
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