Advance Information
Table 40. Erase and Program Operations-S29GL016A Only
Parameter
JEDEC
Std.
Description
Speed Options
90
10
Unit
tAVAV
tWC
Write Cycle Time (Note 11)
Min
90
100
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tWLAX
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high during toggle bit polling Min
0
ns
tDVWH
tDS
Data Setup Time
Min
35
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tCEPH
CE# High during toggle bit polling
Min
20
ns
tOEPH
OE# High during toggle bit polling
Min
20
ns
tGHWL
tGHWL Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
Write Buffer Program Operation (Note 2, Note 3)
Typ
240
tWHWH1
tWHWH1 Single Word Program Operation (Note 2)
Typ
60
µs
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
0.5
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tBUSY
WE# High to RY/BY# Low
Min
90
100
ns
tPOLL
Program Valid before Status Polling
Max
4
µs
Notes:
1. Not 100% tested.
2. See Erase And Programming Performance on page 81 for more information
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16, on page 73
72
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005