Philips Semiconductors
Analog front end for digital video
processors
Preliminary specification
PNX3000
SYMBOL
PARAMETER
CONDITIONS
MIN.
PLL DEMODULATOR; NOTES 4 AND 5
∆fVCO
free-running frequency
offset of VCO
PLL not locked; deviation from
nominal setting
fcr(PLL)
catching range PLL
without SAW filter; referred to
selected IF system frequency
td(ident)
delay time of identification bit LOCK = 1
VIDEO AMPLIFIER OUTPUT: PIN CVBSOUTIF; NOTE 6
Vo(z)
zero signal output level
negative modulation; note 7
positive modulation; note 7
Vo(ts)
Vo(w)
Vo(dem)(p-p)
top sync level
negative modulation
white level
positive modulation
demodulated CVBS output recommended settings for bits
signal (peak-to-peak value) VA1 and VA0; note 8
∆Vo
difference in amplitude
recommended settings for bits
between negative and
VA1 and VA0; note 8
positive modulation
Zo(v)
Ibias(int)
video output impedance
internal bias current of
NPN emitter follower
output transistor
Isource(max)
Bv(−3dB)
maximum source current
bandwidth of demodulated at −3 dB; before sound trap
video output signal
Gdif
differential gain
negative modulation; note 9
positive modulation; note 9
ϕdif
NLvid
Vclamp
Nclamp
differential phase
video non-linearity
white spot clamp level
noise inverter clamping
level
notes 9 and 10
note 11
note 12
Nins
noise inverter insertion
note 12
level
dblue
dyellow
S/N
intermodulation at ‘blue’
intermodulation at ‘yellow’
signal-to-noise ratio
notes 10 and 13
Vo at 0.92 MHz or 1.1 MHz
Vo at 2.66 MHz or 3.3 MHz
notes 10 and 13
Vo at 0.92 MHz or 1.1 MHz
Vo at 2.66 MHz or 3.3 MHz
notes 10 and 14
weighted
unweighted
∆Vrc
residual carrier signal
note 10
−500
±1
−
−
−
1.3
−
1.8
−
−
−
−
6
−
−
−
−
−
−
−
60
60
56
60
−
56
49
−
TYP. MAX. UNIT
−
0
−
−
−
20
3.5
−
1.1
−
1.4
1.5
3.4
−
2.0
2.2
0
15
kHz
MHz
ms
V
V
V
V
V
%
150
250
Ω
0.9
−
mA
−
1
9
−
2
5
3
5
−
5
−
5
3.8
−
0.9
−
2.3
−
mA
MHz
%
%
deg
%
V
V
V
66
−
dB
66
−
dB
62
−
dB
66
−
dB
−
−
60
−
dB
53
−
dB
5.5
−
mV
2004 Oct 04
25