DATA SHEET
PMC-960840
ISSUE 5
PM4388 TOCTL
OCTAL T1 FRAMER
1 FEATURES
• Integrates eight T1 framers in a single device for terminating duplex DS-1
signals.
• Supports SF and ESF format DS-1 signals.
• Supports transfer of PCM data to/from 1.544 MHz system-side devices. Also
supports a fractional T1 system interface with independent ingress/egress
NxDS0 rates. Supports a 2.048 MHz system-side interface without external
clock gapping.
• Provides jitter attenuation in the receive and transmit directions.
• Provides per-DS0 line loopback and per link diagnostic and line loopbacks.
• Provides an integral pattern generator/detector that may be programmed to
generate and detect common pseudo-random or repetitive sequences. The
programmed sequence may be inserted/detected in the entire DS-1 frame, or
on an NxDS0 basis, in both the ingress and egress directions. May be
configured to transmit or detect in only the 7 most significant bits of selected
channels, in order to support fractional T1 loopback codes in an N x 56kbps
fractional T1 setup. Each framer possesses its own independent pattern
generator/detector, and each detector counts pattern errors using a 32-bit
saturating error counter.
• Provides robbed bit signaling extraction and insertion on a per-DS0 basis.
• Provides programmable idle code substitution, data and sign inversion, and
digital milliwatt code insertion on a per-DS0 basis.
• Software compatible with the PM4341A T1XC Single T1 Transceiver and the
PM4344 TQUAD Quad T1 Framer.
• Seamless interface to the PM8313 D3MX single chip M13 multiplex and to
the PM4314 QDSX Quad Line Interface.
• Provides an 8-bit microprocessor bus interface for configuration, control, and
status monitoring.
• Low power 3.3V CMOS technology with 5V tolerant inputs.
• Supports standard 5 signal P1149.1 JTAG boundary scan.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
1