HI-518
Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V; VDD/LLS = GND
(Note 3), Unless Otherwise Specified (Continued)
I+, Current
I-, Current
NOTES:
PARAMETER
TEST
TEMP
-8
-5
CONDITIONS (oC)
MIN
TYP MAX MIN
TYP MAX UNITS
VEN = 2.4V
Full
-
Full
-
-
15
-
-
15
-
-
18
mA
-
18
mA
3. VDD/LLS pin = open or grounded for TTL compatibility. VDD/LLS pin = VDD for CMOS compatibility.
4. At temperatures above 90oC, care must be taken to assure VIN remains at least 1.0V below the VSUPPLY for proper operation.
5. VIN = ±10V, IOUT = -100µA.
6. VIN = 0V, CL = 100pF, enable input pulse = 3V, f = 500kHz.
7. CL = 40pF, RL = 1K, VEN = 0.8V, VIN = 3VRMS, f = 500kHz. Due to the pin to pin capacitance between IN 8/4B and OUT B, channel 8/4B
exhibits 60dB of OFF isolation under the above test conditions.
Test Circuits and Waveforms VDD/LLS = GND, Unless Otherwise Specified
IOUT 100µA
V2
EN
0.8V
OUT
IN
±10V
VIN
OUT
V2
rON = 100µA
±10V
A ID(OFF)
10V
FIGURE 1. ON RESISTANCE TEST CIRCUIT
FIGURE 2. ID(OFF) TEST CIRCUIT (NOTE 8)
IS(OFF) A
±10V
OUT
EN
10V
0.8V
OUT
EN
A2
A0
A ID(ON)
10V
±10V
FIGURE 3. IS(OFF) TEST CIRCUIT (NOTE 8)
50%
3.5V ADDRESS
DRIVE (VA)
0V
+10V
OUTPUT
10%
tA
-10V
2.4V
FIGURE 4. ID(ON) TEST CIRCUIT (NOTE 8)
+15V
V+
VA
50Ω
2.4V
IN 1
A2 / SDS
A1
A0
IN 2-7
IN 8
OUTA
EN
OUTB
VDD/LLS V-
GND
-15V
±10V
10V
10 50
kΩ pF
FIGURE 5A. MEASUREMENT POINTS
FIGURE 5B. TEST CIRCUIT
NOTE:
FIGURE 5. ACCESS TIME
8. Two measurements per channel: ±10V and 10V. (Two measurements per device for ID(OFF) ±10V and 10V.)
4