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FB2033BB View Datasheet(PDF) - Philips Electronics

Part Name
Description
MFG CO.
FB2033BB Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Philips Semiconductors
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
Product specification
FB2033
LIVE INSERTION SPECIFICATIONS
SYMBOL
VBIASV Bias pin voltage
IBIASV Bias pin DC current
VBn
ILM
IHM
IBnPEAK
Bus voltage during pre-bias
Fall current during pre-bias
Rise current during pre-bias
Peak bus current during
insertion
IOLOFF Power up current
tGR Input glitch rejection
PARAMETER
VCC = 0 to 5.25V, Bn = 0 to 2.0V
VCC = 0 to 4.75V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
VCC = 4.5 to 5.5V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
B0 – B8 = 0V, Bias V = 5.0V
B0 – B8 = 2V, Bias V = 4.5 to 5.5V
B0 – B8 = 1V, Bias V = 4.5 to 5.5V
VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V,
Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns
VCC = 0 to 5.25V, OEB0 = 0.8V
VCC = 0 to 2.2V, OEB0 = 0 to 5V
VCC = 5.0V
LIMITS
MIN
NOM
MAX
4.5
5.5
1
10
1.62
2.1
1
-1
10
100
100
1.0
1.35
UNIT
V
mA
µA
V
µA
µA
mA
µA
ns
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
A PORT LIMITS
Tamb = +25°C, VCC = 5V,
CL = 50pF, RL = 500
Tamb = 0 to 70°C,
VCC = 5V±10%,
CL = 50pF, RL = 500
MIN TYP MAX
MIN
MAX
UNIT
fMAX
Maximum clock frequency
Waveform 4
100 150
100
MHz
tPLH
Propagation delay (thru mode)
tPHL
Bn to AOn
Waveform 1, 2
2.2
4.3
6.0
2.0
4.1
6.0
2.0
1.8
7.0
7.0
ns
tPLH
Propagation delay (transparent latch)
tPHL
Bn to AOn
Waveform 1, 2
1.5
4.5
6.5
2.4
4.4
6.5
1.0
2.0
7.5
7.5
ns
tPLH
Propagation delay
tPHL
LCBA to AOn
Waveform 1, 2
2.0
3.8
5.5
2.2
4.3
6.0
1.8
1.7
6.0
6.5
ns
tPLH
Propagation delay
tPHL
SBAn to AOn
Waveform 1, 2
1.4
2.9
5.0
1.4
3.1
5.5
1.0
1.0
6.0
6.5
ns
tPLH
Propagation delay (Loopback mode)
tPHL
AIn to AOn
Waveform 1, 2
2.0
3.8
6.0
2.0
3.9
6.0
2.8
2.3
7.0
7.0
ns
tPLH
Propagation delay (Loopback mode)
tPHL
Loopback to AOn
Waveform 1, 2
1.2
3.4
5.0
1.2
3.2
5.5
1.0
1.0
6.0
6.5
ns
tPZH
Output enable time from High or Low
tPZL
OEA to AOn
Waveform 5, 6
1.0
3.1
5.1
2.6
4.0
5.5
1.0
2.4
5.5
5.8
ns
tPHZ
Output disable time to High or Low
tPLZ
OEA to AOn
Waveform 5, 6
1.0
3.5
5.0
1.0
3.3
4.6
1.7
1.7
5.6
5.2
ns
tTLH
tTHL
tSK(o)
Output transition time, AOn Port
10% to 90%, 90% to 10%
Output to output skew, A port 1
Test Circuit and
Waveforms
Waveform 3
2.0
2.0
0.5
1.0
5.0
5.0
ns
1.5
ns
tSK(p)
Pulse skew 2
tPHL – tPLH MAX
Waveform 2
0.3
1.0
1.5
ns
NOTES:
1. Bn to AOn propagation delays are extended for 5 nanoseconds following B port excursions above 3.1 volts.
2. tPNactual – tPMactualfor any data input to output path compared to any other data input to output path where N and M are either LH or HL.
Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
3. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
1995 May 25
7

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