NXP Semiconductors
6. Pinning information
6.1 Pinning
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
VDD 1
RESET 2
P0_0 3
P0_1 4
P0_2 5
P0_3 6
VDD(IO)0 7
P0_4 8
P0_5 9
P0_6 10
P0_7 11
INT 12
PCA9575PW1
24 SCL
23 SDA
22 P1_0
21 P1_1
20 P1_2
19 P1_3
18 VDD(IO)1
17 P1_4
16 P1_5
15 P1_6
14 P1_7
13 VSS
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Fig 3. Pin configuration for TSSOP24
A0 1
VDD 2
RESET 3
P0_0 4
P0_1 5
P0_2 6
P0_3 7
A1 8
VDD(IO)0 9
P0_4 10
P0_5 11
P0_6 12
P0_7 13
INT 14
PCA9575PW2
28 SCL
27 SDA
26 P1_0
25 P1_1
24 P1_2
23 P1_3
22 A3
21 VDD(IO)1
20 P1_4
19 P1_5
18 P1_6
17 P1_7
16 VSS
15 A2
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Fig 4. Pin configuration for TSSOP28
terminal 1
index area
P0_1 1
P0_2 2
P0_3 3
VDD(IO)0 4
P0_4 5
P0_5 6
PCA9575HF
18 P1_1
17 P1_2
16 P1_3
15 VDD(IO)1
14 P1_4
13 P1_5
Fig 5. Pin configuration for HWQFN24
Transparent top view
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PCA9575_3
Product data sheet
Rev. 03 — 9 November 2009
© NXP B.V. 2009. All rights reserved.
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