NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
data from
shift register
data from
shift register
write
configuration
pulse
write pulse
read pulse
configuration
register
D
Q
FF
CK Q
DQ
FF
CK
output port
register
input port
register
D
Q
FF
CK
VDD(IO)
BUS-HOLD
AND
PULL-UP/PULL-DOWN
CONTROL
100 kΩ
Q1
Q2
ESD
protection
diode
INTERRUPT
MASK
output port
register data
VDD(IO)
P0_0 to P0_7
P1_0 to P1_7
VSS
input port
register data
to INT
data from
shift register
write polarity
pulse
polarity
inversion
register
D
Q
FF
CK
Fig 2. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
polarity
inversion
register data
002aad566
PCA9575_3
Product data sheet
Rev. 03 — 9 November 2009
© NXP B.V. 2009. All rights reserved.
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