PALCE20V8Q-7JI View Datasheet(PDF) - Advanced Micro Devices
Part Name
Description
MFG CO.
PALCE20V8Q-7JI Datasheet PDF : 16 Pages
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AMD
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight
independently configurable macrocells (MC0..MC7).
Each macrocell can be configured as a registered out-
put, combinatorial output, combinatorial I/O, or dedi-
cated input. The programming matrix implements a
programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complemen-
tary outputs to provide user-programmable input signal
polarity. Pins 1 and 13 serve either as array inputs or as
clock (CLK) and output enable (OE) for all flip-flops.
Unused input pins should be tied directly to VCC or GND.
Product terms with all bits unprogrammed (discon-
nected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are
automatically configured from the user’s design specifi-
cation, which can be in a number of formats. The design
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user’s desired function.
The user is given two design options with the
PALCE20V8. First, it can be programmed as an emu-
lated PAL device. This includes the PAL20R8 series
and most 24-pin combinatorial PAL devices. The PAL
device programmer manufacturer will supply device
codes for the standard PAL architectures to be used
with the PALCE20V8. The programmer will program the
PALCE20V8 to the corresponding PAL device architec-
ture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed
directly as a PALCE20V8. Here the user must use the
PALCE20V8 device code. This option provides full utili-
zation of the macrocells, allowing non-standard archi-
tectures to be built.
To
Adjacent
Macrocell
11
11
OE
10
VCC
00
0X
01
10
SL0X
SG1
11
0X
I/OX
DQ
10
SL1X
CLK
Q
10
11
0X
*SG1
SL0X
From
Adjacent
Pin
* In Macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
Figure 1. PALCE20V8 Macrocell
16491D-4
2-158
PALCE20V8 Family
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