M74HC40102 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M74HC40102 Datasheet PDF : 16 Pages
| |||
M74HC40102
FUNCTIONAL DESCRIPTION
This device is an 8-stage presettable synchronous
down counter. Carry Out/Zero Detect (CO/ZD) is
output at the "L" level for the period of 1 bit when
the readout becomes "0". This device adopts
binary coded decimal notation, making setting up
to 99 counts possible.
COUNT OPERATION
At the "H" level of control input of CLEAR, SPE
and APE, the counter carriers out down count
operation one by one at the rise of pulse given to
CLOCK input. Count operation can be inhibited by
setting Carry Input/Clock Enable CI/CE to the "H"
level.
CO/ZD is output at the "L" level when the readout
becomes "0" but is not output even if the readout
becomes "0" when CI/CE is at the "H" level, thus
maintaining the "H" level.
Synchronous cascade operation can be carried
out by using CI/CE input and CO/ZD output.
The contents of count jump to maximum count
(99) if clock is given when the readout is "0".
Therefore, operation of 100-frequency division is
carried out when clock input alone is given without
various kinds of preset operation.
PRESET AND RESET OPERATION
When Clear (CLEAR) input is set to the "L" level,
the readout is set to the maximum count
independently of other inputs. When
Asynchronous Preset Enable (APE) input is set to
the "L" level, readouts given on J0 to J7 can be
preset asynchronously to the counter
independently of inputs other than CLEAR input.
When Synchronous Preset Enable (SPE) is set to
the "L" level the readouts given on J0 to J7 can be
preset to counter synchronously with the rise of
clock. As to these operation mode, refer to the
truth table.
CLEAR
L
H
H
H
H
H
H
H
APE
X
L
L
H
H
H
H
H
INPUTS
SPE
J
TE
X
X
X
X
L
X
X
H
X
L
L
X
L
H
X
L
X
X
H
X
L
H
X
H
CLOCK
X
X
X
X
OUTPUT
Qn + 1
L
L
H
L
H
Qn
Qn
Qn
7/16
Share Link: 