Philips Semiconductors
7-stage binary counter
Product specification
HEF4024B
MSI
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
500 fi + ∑ (foCL) × VDD2
where
10
2100 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
5200 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths
and recovery time for MR.
January 1995
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