PCA1070 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
PCA1070 Datasheet PDF : 36 Pages
| |||
Philips Semiconductors
Multistandard programmable analog
CMOS transmission IC
Product specification
PCA1070
The total gain of the DTMF channel between the DTMF
input and the line LN is as follows:
GDTMF = Gma + 6 (dB)
Default GDTMF = 15 + 6 = 21 dB
The confidence tone gain (DTMF to QR outputs) is:
With symmetrical drive of earpiece GCTs = Gra − 19 (dB)
Default GCTss = −6 − 19 = −25 dB.
At low gain settings (Gra < −10 dB), the confidence tone
gain will be slightly higher than the calculated value. This
is caused by a residual signal.
Programming the gain of the ‘sending prog-amp’ and the
‘rec prog-amp’ is given in Table 13.
The gain of the receiving channel can be programmed
between −19 dB and +11 dB (symmetrical drive) in 1 dB
steps using bit code GRAx (6 bits).
GRAx sets the gain of the ‘rec prog-amp’ (allowed range
Gra = −19 dB to +11 dB; default Gra = −6 dB).
The total gain of the receiving channel is as follows:
Symmetrical drive GRS = Gra (dB)
Default GRS = −6 dB.
Asymmetrical or single-ended drive GRA = GRS − 6 (dB)
Default Gra = −6 − 6 (dB) = −12 dB.
Programming the gain Gra of the ‘rec prog-amp’ is given in
Table 13.
Receiving channel
The gain of the receiving channel is defined between the
line connection LN and the earpiece outputs QR+ and
QR−. Its voltage gain is default −6 dB (differential drive).
The LN terminal accepts receiving signals up to 1 V (RMS)
for THD = 2%. The outputs may be used to connect
dynamic, magnetic or piezoelectric earpieces with
single-ended or differential drive. The load select bit RFC
is set default to logic 1 to guarantee stable operation in
case of a capacitive load (piezoelectric earpiece). With a
resistive load (dynamic capsule) RFC should be set to
logic 0 via the I2C-bus interface to obtain optimum
performance with respect to distortion and bandwidth.
Two levels for hearing protection can be selected via the
I2C-bus interface with control bit HPL.
The earpiece arrangements are illustrated in Fig.6.
Sidetone balance
The PCA1070 has an on-chip anti-sidetone circuit.
An internal balance impedance Zoss can be programmed
via the I2C-bus interface to match the external line
impedance Zline to give optimum sidetone suppression.
Zoss = Rsa + (Rsb // Cs).
Programming the sidetone balance impedance is given in
Tables 14, 15 and 16.
Line current control
The DC line current can be read via the I2C-bus interface.
This information can be used for the adaptation of
transmission parameters (for example line loss
compensation, sidetone balance and DC characteristic).
The bit code LCx as a function of line current is given in
Table 17.
handbook, halfpage
QR+
QR−
(a)
symmetrical
QR+
QR−
VSS
MGE340
(b)
single-ended
Fig.6 Earpiece arrangements.
1997 Jun 20
9
Share Link: 