CY7C4806V25 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY7C4806V25 Datasheet PDF : 30 Pages
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PRELIMINARY
CY7C4808V25
CY7C4806V25
CY7C4804V25
Signal Description
Master Reset (MR)
The FIFO memory of the CY7C480XV25 undergoes a com-
plete reset by taking its associated Master Reset (MR) input
LOW for at least four Port A clock (CLKA) and four Port B clock
(CLKB) LOW-to-HIGH transitions. The Master Reset input can
switch asynchronously to the clocks. A Master Reset initializes
the internal read and write pointers and forces the Full/Input
Ready flag (FF/IR) LOW, the Empty/Output Ready flag
(EF/OR) LOW, the Almost Empty flag (AE) LOW, and the Al-
most Full flag (AF) HIGH. After a Master Reset, the FIFO’s
Full/Input Ready flag is set HIGH after two clock cycles to be-
gin normal operation. A Master Reset must be performed on
the FIFO after power up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MR) input
latches the value of the Big Endian (BE) input, determining the
order by which bytes are transferred through Port B.
A LOW-to-HIGH transition on a FIFO reset (MR) input latches
the values of the Flag Select (FS0, FS1) and Serial Program-
ming Mode (SPM) inputs for choosing the Almost Full and Al-
most Empty offset programming method (see Almost Empty
and Almost Full flag offset programming below).
Partial Reset (PR)
Each of the two FIFO memories of the CY7C480XV25 under-
goes a limited reset by taking its associated Partial Reset (PR)
input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset
inputs can switch asynchronously to the clocks. A Partial Re-
set initializes the internal read and write pointers and forces
the Full/Input Ready flag (FF/IR) LOW, the Empty/Output
Ready flag (EF/OR) LOW, the Almost Empty flag (AE) LOW,
and the Almost Full flag (AF) HIGH. After a Partial Reset, the
FIFO’s Full/Input Ready flag is set HIGH after two clock cycles
to begin normal operation.
Whatever flag offsets, programming method (parallel or seri-
al), and timing mode (FWFT or CY Standard mode) are cur-
rently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be in-
convenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or read from either
one of the ports. This selection determines the order by which
bytes (or short words or words) of data are transferred through
this port. For the following examples, assume that a byte (or
short words or word) bus size has been selected for Port B.
(Note that when Port B is configured for a long-word size, the
Big Endian function has no application and the BE input is a
“don’t care”.)
A HIGH on the BE/FWFT input when the Master Reset (MR)
input goes from LOW to HIGH will select a Big Endian arrange-
ment. When data is moving from Port A to Port B, the most
significant byte (short word/word) of the long-word written to
Port A will be transferred to Port B first; the least significant
byte (short word/word) of the long-word written to Port A will
be transferred to Port B last.
A LOW on the BE/FWFT input when the Master Reset (MR)
input goes from LOW to HIGH will select a Little Endian ar-
rangement. When data is moving from Port A to Port B, the
least significant byte (short word/word) of the long-word writ-
ten to Port A will be transferred to Port B first; the most signif-
icant byte (short word/word) of the long-word written to Port A
will be transferred to Port B last.
After Master Reset, the FWFT select function is active, permit-
ting a choice between two possible timing modes: CY Stan-
dard Mode or First-Word Fall-Through (FWFT) Mode. Once
the Master Reset (MR) input is HIGH, a HIGH on the BE/FWFT
input at the second LOW-to-HIGH transition of CLKA will se-
lect CY Standard Mode. This mode uses the Empty Flag func-
tion (EF) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function (FF)
to indicate whether or not the FIFO memory has any free
space for writing. In CY Standard Mode, every word read from
the FIFO, including the first, must be requested using a formal
read operation.
Once the Master Reset (MR) input is HIGH, a LOW on the
BE/FWFT input LOW-to-HIGH transition of CLKA will select
FWFT Mode. This mode uses the Output Ready function (OR)
to indicate whether or not there is valid data at the data outputs
(B0–79). It also uses the Input Ready function (IR) to indicate
whether or not the FIFO memory has any free space for writ-
ing. In the FWFT mode, the first word written to an empty FIFO
goes directly to data outputs, no read request necessary. Sub-
sequent words must be accessed by performing a formal read
operation.
Following Master Reset, the level applied to the BE/FWFT in-
put to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Two registers in the CY7C480XV25 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port A
Almost Empty flag (AE) offset register is labeled X. The Port B
Almost Full flag (AF) offset register is labeled Y. The index of
each register name corresponds with preset values during the
reset of a FIFO, programmed in parallel using the FIFO’s Port
A data inputs, or programmed in serial using the Serial Data
(SD) input (see Table 2).
To load a FIFO’s Almost Empty flag and Almost Full flag offset
registers with one of the three preset values listed in Table 2,
the Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH tran-
sition of its Master Reset input (MR). For example, to load the
preset value of 64 into X and Y, SPM, FS0, and FS1 must be
HIGH when the FIFO reset (MR) returns HIGH.
To program the X and Y registers from Port A, perform a Mas-
ter Reset with SPM HIGH and FS0 and FS1 LOW during the
LOW-to-HIGH transition of MR. After this reset is complete, the
first two writes to the FIFO do not store data in memory but
load the offset registers in the order Y and X. The Port A data
inputs used by the offset registers are (A0–11), (A0–13), or
(A0–15),for the CY7C480XV25, respectively. The highest num-
bered input is used as the most significant bit of the binary
number in each case. Valid programming values for the regis-
ters range from 0 to 4095 for the CY7C4804V25; 0 to 16383
for the CY7C4806V25; 0 to 65535 for the CY7C4808V25. Be-
fore programming the offset registers, FF/IR is set HIGH.
FIFOs begin normal operation after programming is complete.
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