
MT9162
Data Sheet
Tj
70%
STB
30%
tdda1
Dout 70%
30%
70%
Din
30%
tdda2
tdha1
Bit 1
TDATA1
tho
tsu
Bit 2
Bit 3
TDATA
D1
TDATA/2
TDATA
D2
D3
TDATA
NOTE: Levels refer to% VDD (CMOS I/O)
Figure 6 - SSI Asynchronous Timing Diagram
13
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