MT9045 View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
MFG CO.
MT9045 Datasheet PDF : 34 Pages
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MT9045
Data Sheet
Pin Description (continued)
Pin # Name
Description
16 C1.5o Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
18 LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to
the input reference.
19
C2o Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.
20
C4o Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
21
C19o Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.
22 FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference
(less than 500 ms locking time).
24
IC Internal Connection. Tie low for normal operation.
25
C8o Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.
26
C16o Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384MHz clock.
27
C6o Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
29 HOLD Holdover (CMOS Output). This output goes to a logic high whenever the PLL goes into
OVER holdover mode.
30
PCCi Phase Continuity Control Input (Input). The signal at this pin affects the state changes
between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and
Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o.
See Table 4.
32
NC No connection. Leave open circuit
33,34
IC Internal Connection. Tie low for normal operation.
36
MS2 Mode/Control Select 2 (Input). This input determines the state (Normal, Holdover or
Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See
Table 3.
37
MS1 Mode/Control Select 1 (Input). The logic level at this input is gated in by the rising edge of
F8o. See pin description for MS2. This pin is internally pulled down to VSS.
38 RSEL Reference Source Select (Input). A logic low selects the PRI (primary) reference source as
the input reference signal and a logic high selects the SEC (secondary) input. The logic level
at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled
down to VSS.
39
IC Internal Connection. Tie low for normal operation.
40
FS2 Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four
possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and
SEC inputs. See Table 1.
41
FS1 Frequency Select 1 (Input). See pin description for FS2.
42
IC Internal Connection. Tie low for normal operation.
43 PRIOOR Primary Reference Out Of Capture Range (Output). A logic high at this pin indicates that
the Primary reference is off the nominal frequency by more than ±17 ppm.
4
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