MH8V72AWZJ-5 View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
MFG CO.
MH8V72AWZJ-5
MITSUBISHI ELECTRIC
MH8V72AWZJ-5 Datasheet PDF : 20 Pages
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Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH8V72AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
Limits
-5
-6
Unit
Min
Max
Min
Max
tRWC Read write/read modify write cycle time (Note22) 130
150
ns
tRAS /RAS low pulse width
85
10000
95
10000
ns
tCAS /CAS low pulse width
50
10000
50
10000
ns
tCSH /CAS hold time after /RAS low
85
95
ns
tRSH
tRCS
tCWD
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
50
0
(Note23)
30
50
ns
0
ns
30
ns
tRWD
tAWD
tCWL
tRWL
tWP
Delay time, /RAS low to /W low
Delay time, address to /W low
/CAS hole time after /W low
/RAS hold time after /W low
Write pulse width
(Note23)
65
(Note23)
40
15
15
10
75
ns
45
ns
15
ns
15
ns
10
ns
tDS
Data setup time before /W loe
tDH
Data hold time after /W low
0
0
ns
10
10
ns
tOEH /OE hold time after /W low
10
15
ns
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD ≥tCPWD(min) (for Fast page mode cycle only),
the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is
satisfied,the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate.
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)
Symbol
Parameter
Limits
-5
Min
Max
-6
Min
Max
tPC
Fast page mode read/write cycle time
35
40
tPRWC Fast page mode read write/read modify write cycle time
70
75
tRAS /RAS low pulse width for read write cycle (Note25) 85
51200
100
51200
tCP
/CAS high pulse width
(Note26)
5
10
10
15
tCPRH /RAS hold time after /CAS precharge
30
35
tCPWD Delay time, /CAS precharge to W low
(Note23)
30
35
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.
25: tRAS(min) is specified as two cycles of /CAS input are performed.
26: tCP(max) is specified as a reference point only. If tCP ≥ tCP(max),access time is controlled exclusively by tCAC.
Unit
ns
ns
ns
ns
ns
ns
/CAS before /RAS Refresh Cycle (Note 27)
Symbol
Parameter
tCSR
tCHR
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
Limits
-5
-6
Min
Max
Min
Max
5
10
10
10
10
10
10
10
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh
mode.
Unit
ns
ns
ns
ns
MIT-DS-0093-0.5
MITSUBISHI
ELECTRIC
( 9 / 20 )
26/Feb./1997
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