Truth Table
Clear
L
H
H
H
H HIGH Level (steady-state)
L LOW Level (steady-state)
X Don’t Care
n Transition from LOW-to-HIGH level
Q0 The level of Q before the indicated steady-state input
conditions were established.
Logic Diagram
(Each Flip-Flop)
Inputs
Clock
D
X
X
n
H
n
L
L
X
Outputs
Q
L
H
L
Q0
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