MM74HCT245SJ View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

MFG CO.

MM74HCT245SJ

Octal 3-STATE Transceiver

Fairchild Semiconductor 

February 1984

Revised May 2005

MM74HCT245

Octal 3-STATE Transceiver

General Description

The MM74HCT245 3-STATE bi-directional buffer utilizes

advanced silicon-gate CMOS technology and is intended

for two-way asynchronous communication between data

buses. It has high drive current outputs which enable high

speed operation even when driving large bus capaci-

tances. This circuit possesses the low power consumption

of CMOS circuitry, yet has speeds comparable to low

power Schottky TTL circuits.

This device is TTL input compatible and can drive up to 15

LS-TTL loads, and all inputs are protected from damage

due to static discharge by diodes to VCC and ground.

The MM74HCT245 has one active low enable input (G),

and a direction control (DIR). When the DIR input is HIGH,

data flows from the A inputs to the B outputs. When DIR is

LOW, data flows from B to A.

MM74HCT devices are intended to interface between TTL

and NMOS components and standard CMOS devices.

These parts are also plug-in replacements for LS-TTL

devices and can be used to reduce power consumption in

existing designs.

Features

s TTL input compatible

s 3-STATE outputs for connection to system busses

s High output drive current: 6 mA (min)

s High speed: 16 ns typical propagation delay

s Low power: 80 PA (74HCT Series)

Ordering Code:

Order Number Package Number

Package Description

MM74HCT245WM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HCT245SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HCT245MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HCT245N

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Pin Assignments for DIP, SOIC, SOP and TSSOP

Control

Inputs

G

L

L

H

H HIGH Level

L LOW Level

X Irrelevant

DIR

L

H

X

Operation

245

B data to A bus

A data to B bus

isolation

Top View

© 2005 Fairchild Semiconductor Corporation DS005366

www.fairchildsemi.com

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