LOOP SPECIFICATIONS (VDD = VCC = 2.7 to 5.5 V unless otherwise indicated, TA = – 40 to + 85°C)
Symbol
Parameter
Fig.
Test Condition
No.
Pin Input Sensitivity Range, fin
500 MHz ≤ fin ≤ 2000 MHz
7
fref Input Frequency, REFin Externally Driven in Vin ≥ 400 mV p–p
Reference Mode
2.7 ≤ VDD < 4.5 V 8
4.5 ≤ VDD ≤ 5.5 V
fXTAL Crystal Frequency, Crystal Mode
C1 ≤ 30 pF, C2 ≤ 30 pF, Includes Stray
9
Capacitance
fout Output Frequency, REFout
CL = 20 pF, Vout ≥ 1 V p–p
f
Operating Frequency of the Phase Detectors
10, 12
tw Output Pulse Width (φR, φV, and LD)
fR in Phase with fV, CL = 20 pF, φR and φV
active for LD measurement, **
VPD = 2.7 to 5.5 V
VDD = 2.7 V
VDD = 4.5 V
VDD = 5.5 V
11, 12
tTLH, Output Transition Times (LD, φV, and φR)
tTHL
CL = 20 pF, VPD = 2.7 V,
VDD = VCC = 2.7 V
11, 12
Cin Input Capacitance, REFin
* Power level at the input to the dc block.
** When PDout is active, LD minimum pulse width is approximately 5 ns.
Guaranteed
Operating
Range
Min Max
– 10
4
1.5
20
1.5
30
2
15
dc
10
dc
2
40
120
18
60
14
50
—
80
—
7
Unit
dBm*
MHz
MHz
MHz
MHz
ns
ns
pF
SINE WAVE
GENERATOR
50 Ω
50 Ω PAD
DC
BLOCK
fin OUTPUT A
DEVICE
UNDER
fin TEST
VCC GND VDD
TEST
POINT
(fV)
V+
SINE WAVE
GENERATOR
0.01 µF
REFin OUTPUT A
DEVICE
TEST
POINT
(fR)
Vin
50 Ω
UNDER
TEST
REFout
VCC GND VDD
TEST
POINT
V+
NOTE: Alternately, the 50 Ω pad may be a T network.
Figure 7. Test Circuit
Figure 8. Test Circuit — Reference Mode
TEST
REFin OUTPUT A
POINT
C1
DEVICE UNDER (fR)
TEST
REFout
C2
VCC GND VDD
V+
REFout
1 / f REFout
50%
Figure 10. Switching Waveform
Figure 9. Test Circuit — Crystal Mode
tw
90%
OUTPUT 50% 10%
tTHL
tTLH
Figure 11. Switching Waveform
TEST POINT
DEVICE
UNDER
TEST
CL*
* Includes all probe and
fixture capacitance.
Figure 12. Test Circuit
MOTOROLA
MC145202
7