MC10H210L View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
MC10H210L Datasheet PDF : 6 Pages
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MC10H210
Dual 3−Input 3−Output OR
Gate
Description
The MC10H210 is designed to drive up to six transmission lines
simultaneously. The multiple outputs of this device also allow the wire
ORing of several levels of gating for minimization of gate and package
count.
The ability to control three parallel lines with minimum propagation
delay from a single point makes the MC10H210 particularly useful in
clock distribution applications where minimum clock skew is desired.
Features
• Propagation Delay Average, 1.0 ns Typical
• Power Dissipation, 160 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K™ Compatible
• Pb−Free Packages are Available*
LOGIC DIAGRAM
5
6
2
7
3
4
9
10
12
11
13
14
VCC1 = PINS 1, 15
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
AOUT
3
AOUT
4
AIN
5
AIN
6
AIN
7
VEE
8
16
VCC2
15
VCC1
14
BOUT
13
BOUT
12
BOUT
11
BIN
10
BIN
9
BIN
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
February, 2006 − Rev. 7
http://onsemi.com
MARKING DIAGRAMS*
CDIP−16
L SUFFIX
CASE 620A
16
MC10H210L
AWLYYWW
1
16
16
1
PDIP−16
P SUFFIX
CASE 648
MC10H210P
AWLYYWWG
1
10H210
ALYWG
SOEIAJ−16
CASE 966
1 20
20 1
PLLC−20
FN SUFFIX
CASE 775
10H210G
AWLYYWW
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
MC10H210/D
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