
MC10H644, MC100H644
Q4 VT Q5 GT R
18 17 16 15 14
GT 19
13 VE
Q3 20
12 DE
GT 1
11 VBB
Q2 2
10 DE
GT 3
9 GE
4 5 6 78
Q1 VT Q0 SEL DT
Figure 1. Pinout: PLCC−20 (Top View)
VBB
DE
(ECL)
DE
(ECL)
DT
(TTL)
2:1 MUX
Table 1. PIN DESCRIPTION
PIN
FUNCTION
GT
VT
VE
GE
DE, DE
VBB
DT
Qn, Qn
SEL
R
TTL Ground (0 V)
TTL VCC (+5.0 V)
ECL VCC (+5.0 V)
ECL Ground (0 V)
ECL Signal Input (positive ECL)
VBB Reference Output
TTL Signal Input
Signal Outputs (TTL)
Input Select (TTL)
Reset (TTL)
*Skews are specified for Identical Edges
TTL OUTPUTS
Q0
÷2
Q1
Q2
SEL
(TTL)
Q3
÷4
Q4
R
(TTL)
Q5
Figure 2. Logic Diagram
http://onsemi.com
2