MC100E136 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
MC100E136 Datasheet PDF : 12 Pages
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CLOCK
S1
MC10E136, MC100E136
LOAD
100100
100011
100010
000011
• ••
000010
000001
000000
LOAD
•••
COUT
•••
DIVIDE BY 37
Figure 6. Programmable Divider Waveforms
The exercise of building a programmable divider then
becomes simply determining what value to load into the
counter to accomplish the desired division. Since the load
operation requires a clock pulse, to divide by N, N−1 must
be loaded into the counter. A single E136 device is capable
of divide ratios of 2 to 64 inclusive, Table 1 outlines the load
values for the various divide ratios. Figure 4 presents the
waveforms resulting from a divide by 37 operation. Note
that the availability of the COUT complementary output
COUT allows the user to choose the polarity of the divide by
output.
For single device programmable counters the E016
counter is probably a better choice than the E136. The E016
has an internal feedback to control the reloading of the
counter, this not only simplifies board design but also will
result in a faster maximum count frequency.
For programmable dividers of larger than 8 bits the
superiority of the E016 diminishes, and in fact for very wide
dividers the E136 will provide the capability of a faster count
frequency. This potential is a result of the cascading features
mentioned previously in this document. Figure 5 shows the
architecture of a 24-bit programmable divider implemented
using E136 counters. Note the need for one external gate to
control the loading of the entire counter chain. An ideal
device for the external gating of this architecture would be
the 4-input OR function in the 8-lead SOIC ECLinPS Lite™
family. However the final decision as to what device to use
for the external gating requires a balancing of performance
needs, cost and available board space. Note that because of
the need for external gating the maximum count frequency
of a given sized programmable divider will be less than that
of a single cascaded counter.
Q0 −> Q5
Q0 −> Q5
CLOCK
“LO”
“LO”
CLK
S1
LSB
CIN
CLIN
COUT
CLOUT
CLK
S1
“LO”
CIN
CLIN
COUT
CLOUT
D0 −> D5
D0 −> D5
Q0 −> Q5
CLK
S1
CIN
CLIN
COUT
CLOUT
D0 −> D5
Q0 −> Q5
CLK
S1
MSB
CIN
CLIN
COUT
CLOUT
D0 −> D5
OUT
Figure 7. 24-bit Programmable Divider Architecture
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