MAX9310A View Datasheet(PDF) - Maxim Integrated
Part Name
Description
MFG CO.
MAX9310A
Maxim Integrated
MAX9310A Datasheet PDF : 11 Pages
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1:5 Clock Driver with Selectable LVPECL
Inputs/Single-Ended Inputs and LVDS Outputs
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18, 20
19
NAME
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
GND
CLKSEL
CLK0
CLK0
VBB
CLK1
CLK1
VCC
EN
Pin Description
FUNCTION
Noninverting Differential Output 0. Typically terminated with 100Ω to Q0.
Inverting Differential Output 0. Typically terminated with 100Ω to Q0.
Noninverting Differential Output 1. Typically terminated with 100Ω to Q1.
Inverting Differential Output 1. Typically terminated with 100Ω to Q1.
Noninverting Differential Output 2. Typically terminated with 100Ω to Q2.
Inverting Differential Output 2. Typically terminated with 100Ω to Q2.
Noninverting Differential Output 3. Typically terminated with 100Ω to Q3.
Inverting Differential Output 3. Typically terminated with 100Ω to Q3.
Noninverting Differential Output 4. Typically terminated with 100Ω to Q4.
Inverting Differential Output 4. Typically terminated with 100Ω to Q4.
Ground
Clock Select Input. Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1,
CLK1 input. The CLKSEL threshold is equal to VBB. Internal 60kΩ pulldown to GND.
Noninverting Differential Clock Input 0. Internal 75kΩ pulldown to GND.
Inverting Differential Clock Input 0. Internal 75kΩ pullup to VCC and 75kΩ pulldown to GND.
Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a
reference for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to
VCC; otherwise, leave open.
Noninverting Differential Input 1. Internal 75kΩ pulldown to GND.
Inverting Differential Input 1. Internal 75kΩ pullup to VCC and 75kΩ pulldown to GND.
Positive Supply Voltage. Bypass VCC to GND with 0.1µF and 0.01µF ceramic capacitors. Place
the capacitors as close to the device as possible with the smaller value capacitor closest to the
device.
Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected
clock input when EN is low. Outputs are synchronously driven to a differential low state on the
falling edge of the selected clock input when EN is high. Internal 60kΩ pulldown to GND
(Figure 3).
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